Low-cache high-deterministic mesochronous dual-clock FIFO buffer

Mesochronous is widely adopted due to its abilities to simplify timing closure and enhance modularity. Increasingly, various application scenarios demand improved performance, requiring higher levels of real-time capability and determinism. There is a relationship where clock frequency is the same, and phase is fixed but unknown between mesochronous modules. Cross-clock domain issues must be considered when transferring data between two modules. In this brief, we introduce a novel mesochronous dual-clock first-input-first-output (FIFO) buffer. This design adopts suitable transmission technologies based on signal characteristics to address cross-clock domain issues effectively. Moreover, it adopts a tightly coupled strategy for data read and write, which significantly minimizes fluctuations in the time from data writing to reading and simplifies the overall system design. Compared to existing dual-clock asynchronous FIFOs, the proposed design boasts the advantages of low resource costs, shallow buffer depth, and high determinism in forward latency. Extensive analyses and actual system tests have been conducted on it, validating its effectiveness.