SHAREDD: Sharing of Test Data and Design-for-Testability Logic for Transition Fault Tests under Standard Scan

High reliability requirements in certain systems are combined with constraints on test overheads, including test data volume, test application time and design-for-testability ( DFT ) logic. The overheads can be reduced if they are shared among different types of tests and optimized together. Several observations are combined in this article to allow sharing of overheads when the goal is to produce a compact transition fault test set with a high fault coverage and low storage requirements supported by DFT logic under standard scan. Based on these observations, the iterative procedure described in this article optimizes four parameters together: (1) the transition fault coverage, (2) the number of stored tests, (3) the number of applied tests, and (4) the size of the DFT logic. Experimental results for benchmark circuits in an academic environment demonstrate the effectiveness of the procedure.

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Publication Details

Journal
ACM Transactions on Design Automation of Electronic Systems
Published
2024-09-28
DOI
https://doi.org/10.1145/3698198
Citations
1
Primary Topic
VLSI and Analog Circuit Testing
Type
article
Field-Weighted Citation Impact
0.49
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article

SHAREDD: Sharing of Test Data and Design-for-Testability Logic for Transition Fault Tests under Standard Scan

Irith Pomeranz
1 citations
ACM Transactions on Design Automation of Electronic Systems
VLSI and Analog Circuit Testing
0.49
article

SHAREDD: Sharing of Test Data and Design-for-Testability Logic for Transition Fault Tests under Standard Scan

Irith Pomeranz
article en
1 citations

Abstract

High reliability requirements in certain systems are combined with constraints on test overheads, including test data volume, test application time and design-for-testability ( DFT ) logic. The overheads can be reduced if they are shared among different types of tests and optimized together. Several observations are combined in this article to allow sharing of overheads when the goal is to produce a compact transition fault test set with a high fault coverage and low storage requirements supported by DFT logic under standard scan. Based on these observations, the iterative procedure described in this article optimizes four parameters together: (1) the transition fault coverage, (2) the number of stored tests, (3) the number of applied tests, and (4) the size of the DFT logic. Experimental results for benchmark circuits in an academic environment demonstrate the effectiveness of the procedure.

ACM Transactions on Design Automation of Electronic SystemsVol. 30(1)
Purdue University West Lafayette (US)
Openalex Percentile: Top 37%
VLSI and Analog Circuit Testing
0.49
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