200 mm Wafer Level Characterization at 2 K of Si/SiGe Field-Effect Transistors

Si/SiGe has proven to be an excellent spin qubit platform, but industrial production of large-scale spin-qubit chips is missing. We use field effect transistors (FETs) to monitor and develop the quality of the fabrication process on 200 mm wafers at 2 K using a cryogenic wafer prober (CWP). This mass-characterization technique provides statistics on device performance. We observe variations in drain off current and gate threshold voltage of 213 FETs. These variations are related to bias voltage conditions during CWP cooldown, which differ from qubit chip cooldown. To address this, a new FET structure with an additional top gate is introduced, effectively suppressing unintentional charge accumulations. This eliminates drain off currents and improves homogeneity of FET characteristics at 2 K. Our results highlight significant impact of bias conditions during qubit chip cooldown, which, if not accounted for in the qubit chip design, can lead to incorrect conclusions when using CWP.