Demonstration of VGAA-TFETs using InAs/Si Heterojunction on SOI substrate

Tunnel field-effect transistors (TFETs) are expected to be used as a next-generation low-voltage switching device. The TFETs can lower the subthreshold slope (SS) below the physical limit (SS = 60 mV/dec at room temperature) in conventional MOSFETs. Here we demonstrated InAs nanowire (NW)/Si heterojunction vertical gate-all-around (VGAA) TFETs on silicon-on-insulator (SOI) (111) substrates toward vertical integrated circuit applications. The vertical InAs NW channels were grown by selective-area growth on thin SOI(111) substrates.

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Publication Details

Journal
ECS Transactions
Published
2024-09-27
DOI
https://doi.org/10.1149/11402.0171ecst
Citations
1
Primary Topic
Advancements in Semiconductor Devices and Circuit Design
Type
article
Field-Weighted Citation Impact
0.21
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Demonstration of VGAA-TFETs using InAs/Si Heterojunction on SOI substrate

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1 citations
ECS Transactions
Advancements in Semiconductor Devices and Circuit Design
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article

Demonstration of VGAA-TFETs using InAs/Si Heterojunction on SOI substrate

Katsuhiro Tomioka, Junichi Motohisa, Ziye Zheng, Yuki Takeda, Yuki Azuma
article en
1 citations

Abstract

Tunnel field-effect transistors (TFETs) are expected to be used as a next-generation low-voltage switching device. The TFETs can lower the subthreshold slope (SS) below the physical limit (SS = 60 mV/dec at room temperature) in conventional MOSFETs. Here we demonstrated InAs nanowire (NW)/Si heterojunction vertical gate-all-around (VGAA) TFETs on silicon-on-insulator (SOI) (111) substrates toward vertical integrated circuit applications. The vertical InAs NW channels were grown by selective-area growth on thin SOI(111) substrates.

ECS TransactionsVol. 114(2)
Openalex Percentile: Top 48%
Advancements in Semiconductor Devices and Circuit Design
0.21
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