Low-Temperature Selective Si:As Epitaxy

A selective low-temperature Si:As (LT-SiAs) process is presented which utilizes cyclic deposition-etch (CDE) at <450 o C. Selectivity against SiN and SiO x dielectrics and crystallinity are confirmed on gate-all-around (GAA) patterned structures. Hall measurements on blanket wafers show a resistivity minimum of 0.42 mΩ-cm at ~1.7% As for selective LT-SiAs. Secondary-ion mass spectroscopy (SIMS) profiles of P and As diffusion into intrinsic Si (i-Si) for LT-SiP/LT-SiAs/i-Si and LT-SiP/i-Si stacks show >2× benefit of using LT-SiAs spacers to minimize dopant diffusion for as-deposited, soak-annealed and spike-annealed samples. Improvement is attributed to relatively limited diffusivity of As in Si versus P and the lower As concentration needed for LT-SiAs layer to achieve minimum resistivity relative to LT-SiP (~3%). Lastly, a comparison of LT-SiAs and high-temperature Si:As (HT-SiAs) shows a ~2× reduction of As diffusion into i-Si for LT-SiAs at length scales of >10nm.