Design of reliable and fast schmitt trigger 10T SRAM cells using in-memory computing

Abstract Microprocessors, integrated data storage systems, and cache memories are just a few applications that can benefit from SRAM. Computing In memory provides a solution for the von Neumann bottleneck problems. Simultaneously, it removes needless repeated data transmission between CPU and memory. Schmitt trigger was utilized for energy-efficient operation to get high reading and writing capacity. Two cross-coupled inverters with a transistor in between increase the design writing process. Furthermore, voltage boost logic is prioritized to maximize the node capacity. Using two dummy columns and dummy rows in RAM, the Replica technique controls the flow of signals via the core. The simulated results are compared to the designs that already exist. The simulation results show that the leakage power of the proposed design is 0.080µw at 0.6 volts. The WSNM of the proposed cell is twice that of SEDF10T, which can be helpful for high-performance computing applications.