Hot Carrier Degradation-Induced Variability in Different Lightly Doped Drain Processes: From Transistors to SRAM Cells

In this work, the impact of lightly doped drain (LDD) implantation doses on hot carrier degradation (HCD) variability behaviors has been studied for transistors and static random access memory (SRAM) cells. It is found that threshold voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {T}}$ </tex-math></inline-formula>) variability is enhanced, while the saturation current (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {D}}$ </tex-math></inline-formula>) variability is suppressed for n-type MOSFETs (n-MOSFETs) and p-type MOSFETs (p-MOSFETs) during HCD. Nonuniform trap generation and the current self-convergence mechanism are used to explain the reason for variability, respectively. Devices fabricated at higher LDD doses have lower variability, which is attributed to improved quasi-ballistic transport characteristics. Furthermore, the impacts of HCD on the static noise margin (SNM) variability of SRAM cells in the hold and read state are also inhibited with the increased LDD doses due to the descending variability in individual transistors. Therefore, LDD process optimization is beneficial for transistors and circuits against HCD variability without additional design margin.