Design and Analysis of seven multilevel Cascaded H-Bridge inverter controlled by FPGA

This research focuses on the design and analysis of a seven multilevel cascaded H-Bridge CHB inverter system, with particular emphasis on its control mechanism implemented using Field-Programmable Gate Array (FPGA) behavioral modeling, very high speed integrated circuit hardware description language (VHDL) code, which is created and verified with the Xilinx Integrated Synthesis Environment ISE 14.7 software. The proposed system employs seven cascaded H-Bridge inverters to achieve higher voltage levels and better waveform with lower Total Harmonic Distortion (THD) compared to traditional inverters. To demonstrate this concept, the entire system has been examined and simulated using the MATLAB/Simulink software package. Different values of THDs, Vrms and voltage waveforms have been achieved. The experimental values were compared with that achieved in simulation, and the comparison proved that the results meet the expectations.