Performance analysis of meta-heuristic optimization techniques for multi-objective VLSI circuit partitioning

Abstract The efficiency of various stages of physical design in the Very Large Scale Integration (VLSI) circuit can be enhanced by using multi-objective optimization techniques. The circuit is partitioned into a set of modules at the beginning of the physical design phase. All subsequent physical design stages, like floor planning, placement, pin configuration, and routing etc., are influenced by the outcome of the circuit partitioning method being used. The efficiency of the partitioning method controls the quality of ultimate architecture. The efficiency achieved by the final product may be decreased by incorrect partitioning. This study compares the effectiveness of four Meta-heuristic optimization methods include the Genetic Algorithm (GA),Satin Bowered Bird (SBO), Particle Swarm Optimization (PSO), Simulated Annealing (SA) — in terms of number of net cut, duration of sleeping mode, and efficiency in power consumption. This experiment achieves K-way partitioning of the circuit that minimizes net cuts as well as maximizes sleep duration simultaneously, by evaluating optimization function. Solutions developed using GA, SBO and PSO consistently surpass those acquired using SA with respect to quality of optimal solution. The average optimum net cut and sleep duration achieved by this experiment are 10.7 and 9.9 in GA ; 11.5 and 12.3 in SBO , 11.80 and 9.10 in PSO; and 16.8 and 6.7 in SA based method respectively. This research resulted in a considerable reduction in power consumption, with the system's average power efficiency achieved by 21.6%, 26.84%, 19.85%, and 14.62%, respectively, in GA, SBO , PSO, and SA based optimizations. The experimental results are compared with a recent publication and proposed GA, SBO, and PSO based methods achieve 18.75%, 4.17%, and 1.04% improvement in terms of average net cut respectively. The proposed GA, SBO, PSO and SA also achieve 44.90%, 51.30%, 40.05%, and 18.60% improvement in terms of average power efficiency.

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Journal
Engineering Research Express
Published
2024-09-26
DOI
https://doi.org/10.1088/2631-8695/ad8068
Primary Topic
VLSI and FPGA Design Techniques
Type
article
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Performance analysis of meta-heuristic optimization techniques for multi-objective VLSI circuit partitioning

Sharadindu Roy, Siddhartha Banerjee
Engineering Research Express
VLSI and FPGA Design Techniques
article

Performance analysis of meta-heuristic optimization techniques for multi-objective VLSI circuit partitioning

Sharadindu Roy, Siddhartha Banerjee
article en

Abstract

Abstract The efficiency of various stages of physical design in the Very Large Scale Integration (VLSI) circuit can be enhanced by using multi-objective optimization techniques. The circuit is partitioned into a set of modules at the beginning of the physical design phase. All subsequent physical design stages, like floor planning, placement, pin configuration, and routing etc., are influenced by the outcome of the circuit partitioning method being used. The efficiency of the partitioning method controls the quality of ultimate architecture. The efficiency achieved by the final product may be decreased by incorrect partitioning. This study compares the effectiveness of four Meta-heuristic optimization methods include the Genetic Algorithm (GA),Satin Bowered Bird (SBO), Particle Swarm Optimization (PSO), Simulated Annealing (SA) — in terms of number of net cut, duration of sleeping mode, and efficiency in power consumption. This experiment achieves K-way partitioning of the circuit that minimizes net cuts as well as maximizes sleep duration simultaneously, by evaluating optimization function. Solutions developed using GA, SBO and PSO consistently surpass those acquired using SA with respect to quality of optimal solution. The average optimum net cut and sleep duration achieved by this experiment are 10.7 and 9.9 in GA ; 11.5 and 12.3 in SBO , 11.80 and 9.10 in PSO; and 16.8 and 6.7 in SA based method respectively. This research resulted in a considerable reduction in power consumption, with the system's average power efficiency achieved by 21.6%, 26.84%, 19.85%, and 14.62%, respectively, in GA, SBO , PSO, and SA based optimizations. The experimental results are compared with a recent publication and proposed GA, SBO, and PSO based methods achieve 18.75%, 4.17%, and 1.04% improvement in terms of average net cut respectively. The proposed GA, SBO, PSO and SA also achieve 44.90%, 51.30%, 40.05%, and 18.60% improvement in terms of average power efficiency.

Engineering Research Express
Ramakrishna Mission Vidyamandira (IN)
Openalex Percentile: Top 86%
VLSI and FPGA Design Techniques
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Performance analysis of meta-heuristic optimization techniques for multi-objective VLSI circuit partitioning — Sharadindu Roy, Siddhartha Banerjee · Engineering Research Express (2024) | TGRS Research Map | TGRS