Preparation of new Cu-Gr composite materials for future interconnects by PECVD

<sec><p indent="0mm">The reduction in the size of interconnects at the rear end presents Cu with obstacles like resistivity, electromigration, and RC delay. The combination of Cu and graphene, known as Cu-Gr, offers a solution. It lowers the resistivity of Cu wires, enhances their current density, and provides better resistance to migration. This innovation effectively tackles the existing issues with pure Cu interconnects. Additionally, the plasma enhanced chemical vaper deposition (PECVD) technique offers a practical method for producing graphene at lower temperatures, in line with the current manufacturing process for silicon-based integrated circuits. </sec><sec> The Cu-Gr composites were fabricated as follows. Initially, <sc>100 nm</sc> thick Cu was deposited on the Si/SiO₂ substrate using physical vapor deposition (PVD) technology. Subsequently, graphene was applied to the Cu surface using a PECVD process. Before deposition, the sample was heated to 600℃ in a low-pressure environment. This was succeeded by radio frequency cleaning, where Ar was utilized to enhance the flatness and wettability of the Cu surface. Afterward, hydrogen and methane were introduced as process gases to deposit graphene under different substrate bias pressures. Upon completion of the growth, the samples were cooled down to 200℃ in Ar and returned to the injection chamber. </sec><sec> This paper mainly studied the impact of substrate bias on graphene deposited on Cu via the PECVD process. It also investigated the electrical conductivity of Cu-Gr before and after heat treatment at 350℃, as well as its thermal stress in very large scale integration circuit (VLSI) interconnections using ANSYS. The principal discussions and conclusions are presented below. </sec><sec> (1) Raman spectroscopy analysis confirmed the successful synthesis of graphene structures on Cu substrates under both 75 and <sc>100 V</sc> substrate biases. Notably, when biased at <sc>75 V,</sc> the graphene structures exhibited a reduced number of layers and a lower defect density, indicative of improved quality. Atomic force microscope (AFM) study further showed that the surface roughness of the samples prepared at <sc>75 V</sc> bias was low and the morphology was relatively smooth. Additionally, scanning electron microscope (SEM) examinations revealed that the average sizes of carbon particles on the sample surfaces prepared at 75 and <sc>100 V</sc> biases were comparable, with measurements of 50.46 and <sc>49.63 nm,</sc> respectively. This phenomenon can be rationalized by the diminished activity of the Cu substrate at lower temperatures, which constrains the diffusion kinetics of carbon atoms, thus leading to comparable particle sizes under both bias conditions. </sec><sec> (2) The Cu-Gr was thermally annealed at 350℃. The results showed that the conductivity of Cu-Gr was the highest when the substrate was biased at <sc>75 V,</sc> which was <sc>6.17×10⁷ S/m.</sc> Compared with the conductivity of Cu before annealing, the conductivity of Cu was increased by 12.64%. After heat treatment, the conductivity of Cu-Gr was further improved due to the increase of the grain size on the surface of Cu and the improvement of carbon film structures on the surface of Cu, and reached the maximum value of <sc>6.62×10⁷ S/m</sc> when the substrate bias was <sc>50 V.</sc> Compared with the electrical conductivity of Cu after annealing, the electrical conductivity of Cu was increased by 12.75%. </sec><sec> (3) The Cu-Gr composites in VLSI interconnects generated the maximum thermal stress near the through-hole, with a value of <sc>35.8 MPa.</sc> The maximum elastic strain occurred at the interface of the upper layer of Cu in contact with graphene with a value of 1.1×10⁻⁴. Therefore, further improvement of the interfacial contact between Cu and graphene and optimization of the structural design of complex wiring locations are required to improve the thermal stability of the interconnect structure. </sec>