Design and Implementation of the PHaSE Core: Establishing Hardware Roots of Trust for Safety-Critical Embedded Devices

The assessment of cybersecurity standards for safety-critical embedded systems has gained momentum across the aerospace, medical, defense, and automotive industries. A key challenge in complying with these standards is establishing robust Hardware Roots of Trust that account for evolving threats and malicious hardware changes. This research outlines the development of the Programmable Hardware Siloed Engine (PHaSE) core, integrated within an FPGA to act as an improvement over Trusted Platform Modules (TPMs). The design will support secure boot, ensure confidentiality, offer tamper resistance, and establish security enclaves. To assess its functionality, resource utilization during secure boot is analyzed whilst benchmarking it against commercial TPMs.