Creating a Logic Divider Based on BCD and Utilizing the Vedic Direct Flag Method

Reversible logic has potential for a variety of applications demanding low energy usage since it prevents information loss and energy waste. The purpose of this work is to design a new Vedic divider circuit with reversible gates. Efficiency in quantum and ASIC parameters is demonstrated by the Reversible Direct Flag Vedic Division Method (RDFVDM), which has been devised. Block-level reversible gates are used in the RDFVDM to provide benefits including lower quantum costs and less trash outputs. The performance of Cadence EDA Tool is validated by simulation trials. Based on a comparative examination utilizing current methodologies, RDFVDM performs better than comparable designs. Interestingly, it improves energy usage by 26%. Moreover, RDFVDM performs exceptionally well in terms of quantum cost while employing the RSA cryptographic technique, efficiently managing 1276,293 constant inputs and 311 garbage outputs.