Thermal-Aware Test Scheduling with Floor planning for Three-Dimensional Stacked Integrated Circuit

Testing a three-dimensional stacked integrated circuit (3D-SIC) remains a challenging problem, as generating an optimized test schedule to minimize test time is complicated due to the numerous variables involved. Accessing upper dies is only feasible through the bottom die, necessitating the extension of Test Access Mechanisms (TAMs) via Through-Silicon Vias (TSVs). Limited primary I/O pins, TSVs, and TAM width require efficient resource allocation. Thermal management is crucial due to high core power consumption and uneven distribution, which pose the risk of overheating. Advanced concurrent test scheduling is essential to effectively allocate resources and maintain power and temperature limits. This research proposes thermal-aware test scheduling optimization combined with floor planning for 3D-SICs, aiming to minimize test schedule time while addressing resource and power constraints. Experimental results using several ITC’02 benchmark circuits demonstrate an average estimated improvement of 0.2% in test schedule time when utilizing test scheduling with floor planning compared to test scheduling without floor planning.