A Low Power Scan Cell Design using FreePDK3

Test power is always a significant challenge for test engineers as the power that is dissipated has a serious negative impact on the computer chip reliability. This paper introduces a low power scan cell with efficient state preserving and gating logic to mitigate the negative impact from the test power consumption and unnecessary switching in scan-based designs, particularly during shifting mode. Our experimental results have demonstrated that our proposed scan achieves significant reduction of ~48% in total average power compared to the conventional scan cells, as well as reduction of ~38% in most of the shift cycles when compared to one of the prevalent existing gating architectures, FLS. In summary, this innovative approach presents a promising solution for reducing test power consumption and unnecessary switching in scan-based designs, particularly during shift mode, while maintaining efficiency and minimizing impact on peak power during capture cycles.