Development of a PVT Verification Methodology for Robust Ultra-Low Power Dynamic Comparators

Achieving high manufacturing yield for high-resolution successive approximation register (SAR) analog-to-digital converters (ADCs) faces significant challenges due to variations in oxide thickness and dopant concentration during fabrication. These variations can lead to metastability errors, impacting performance and reliability. This paper presents a novel verification method designed to evaluate the performance of a proposed double-tail dynamic comparator circuit in practical scenarios. A dedicated test scheme is introduced to detect and validate worst-case input voltage transitions across 45 process, voltage, and temperature (PVT) corner simulations, considering variations in VDD, operating temperature, and fabrication processes. The proposed PVT test scheme has been implemented and validated on both the JRR1 comparator and the conventional Double-tail comparator, successfully identifying metastability errors in specific test corner simulations. The results demonstrate the effectiveness of the test scheme in assessing delay and power performance, highlighting its potential to ensure high manufacturing yield and reliability in SAR ADC designs.