Reliability Consequence of using Optimal Gbit Flash Memory based PWM Inverters

The Gbit-size Flash Memory based Pulse Width Modulation (PWM) algorithms for three-phase inverters differ from the conventional counter-based implementation since they follow a pre-programmed optimal PWM pattern. At a fixed sampling interval, each position within the complex plane may correspond to a different sequence of states or pulse structure. The simultaneous optimization of harmonics and power loss was demonstrated with Gbit-size Flash Memory based Pulse Width Modulation (PWM) algorithms. This allows for lifetime and reliability improvement. This paper offers lifetime and reliability calculation for the Gbit-size Flash Memory based Pulse Width Modulation (PWM) algorithms showing their advantage brought with reduction of thermal stress.