Memory Grouping for the Built-In Self-Test of Three-Dimensional Integrated Circuits

As the complexity of circuit design continues to grow, the development of three-dimensional (3D) integrated circuit (IC) technology has become increasingly vital. While 3D ICs offer faster signal transmission speeds and lower power consumption compared with traditional two-dimensional (2D) ICs, they also pose greater challenges in manufacturing and testing. In memory testing, traditional 2D ICs require only a single testing stage, whereas 3D ICs involve both prebond and postbond testing stages, complicating the memory grouping process. Most existing memory grouping algorithms focus on testing 2D ICs. While one study addressed the memory grouping problem for 3D IC testing, it did not consider the impact of test scheduling. In contrast, our approach incorporates test scheduling into the memory grouping process, resulting in a reduction in BIST area overhead. Experimental results demonstrate that our method reduces built-in self-test circuit area overhead by an average of 10.28% compared with those in the existing literature.