A 275 μ W 81.5 dB-SNDR and 200 kS/s CT IDSM With an AC-OSA-Based Integrator Using CNRS and FIR DACs

This brief presents an energy-efficient continuous-time incremental delta-sigma modulator (CT IDSM), where the first integrator employs a fourth-order feedforward-compensated amplifier based on an AC-coupled OTA-stacking amplifier (AC-OSA) and utilizes a charge neutralization reset scheme (CNRS). Extending the AC-OSA to incremental structures significantly improves the energy efficiency of the ADC. The core innovation is the use of CNRS for periodic resets, addressing common-mode (CM) disturbances and incomplete differential-mode (DM) signal resets caused by the conventional shorted integration capacitor scheme. Additionally, to enhance area and power efficiency when using high-tap FIR DACs in CT IDSMs, we propose an excess-loop-delay compensation (ELDC) FIR DAC suitable for single-bit (SB) architectures. A third-order single-loop SB CT IDSM with an eight-tap FIR DAC is fabricated in a 65nm CMOS process and achieves SNDR, SNR, and DR values of 81.5dB, 81.8dB, and 85dB, respectively at a Nyquist conversion rate of 200kS/s. The core area is 0.227mm2, and the ADC consumes <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$275{\mu }$ </tex-math></inline-formula>W. The Schreier (SNDR) figure-of-merit (FoM) is 167.1dB.