A Thermal and Power Integrity Co-Optimization Framework for 2.5-D Integrated Microsystem

Thermal issues and power integrity problems have long been recognized as critical challenges in the design of 2.5-D integrated microsystems. In this paper, a thermal and power integrity co-optimization framework, consisting of a sequential two-stage design and driven by the improved adaptive genetic algorithm, is proposed. In the first stage, the thermally-aware placement, comprehending key design indexes encompassing area, peak temperature, temperature uniformity, and wire routing constrained by multicommodity flow constraints of multi-dies, is addressed. In the second stage, the transmission matrix method is first utilized to characterize the impedance of the hierarchic power delivery network based on the determined chip architecture from the first stage. Then, the initial impedance of the observed port, directly correlated with simultaneous switching noise, is reduced by the layout optimization of on-chip decoupling capacitances. Following this, a benchmark case is established to validate the design framework and its embedded algorithm from multiple perspectives. The results demonstrate that the proposed framework is capable of generating superior solutions compared to mainstream algorithms. Additionally, the proposed design methodology is compared with that of the state-of-the-art studies, revealing that this work bridges the thermal and power integrity domains. This accomplishment provides a novel design paradigm of electronic design automation tools targeting large-scale and highly complex 2.5-D integrated microsystems in the future.