Design and Analysis of Divide-by-4 Injection-Locked Frequency Divider Using Gain-Boosting Injection Balun and Dual Linear Mixer Techniques

We demonstrate the design and analysis of a K-band (18-27 GHz) divide-by-4 injection-locked frequency-divider (ILFD4) in 90 nm CMOS. A wideband balun is used for converting the single-ended injection signal to differential signals. The balun attains 9 dB gain boosting due to the LC-series-peaking at its differential outputs. Instead of the common topology of the body connected to the source, the injection transistors adopt the topology of the body connected to the gate through a large body floating resistance RB of 2.2 k<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula>, i.e., DTMOS-with-RB topology, to enhance their output signals. This leads to 11 dBm (from −29 to −40 dBm) input sensitivity enhancement of the ILFD4 (with output buffers). Divide-by-4 with 8-phase fundamental frequency (f0) output is achieved using the technique of dual linear mixer, i.e., dual linear divide-by-2. The first linear divide-by-2 with differential-quadrature (I/Q) 4-phase 2f0 outputs is performed by the direct-injection of ±4f0 signals to the differential injection transistors (to mix with their fundamental frequency signal at 2f0). The second linear divide-by-2 with 8-phase f0 outputs is carried out by the tail-injection of differential I/Q 4-phase 2f0 signals to the cross-connected four-stage differential ring oscillator (to mix with their fundamental frequency signal at f0). Due to the inherent divide-by-4 feature of the dual linear mixer topology, strong 8-phase divide-by-4 outputs are obtained. In addition to the first-stage FD of a K-band phase-locked loop, the circuit can also be used to provide the required differential-I/Q LO signals (for I/Q modulation and demodulation) of a 28 GHz 5G phased-array transceiver. The ILFD4 consumes 7.2 mW (at VDD of 1 V) and achieves input sensitivity of −40 dBm, locking range (LR) of 52.1% (12.2-20.8 GHz), and the first and second figure-of-merits of 7.24 mW−1 and 3.31, respectively, one of the best results ever reported for CMOS ILFD4s with similar operation frequency. For VDD of 1-1.5 V, a wide LR of 67.4% (12.2-24.6 GHz) is attained. The ILFD4 core only occupies a small chip area of 0.037 mm2.