A High Linearity ADC Front-End Circuit for Single-Ended Inputs

This paper presents a high linearity ADC front-end circuit for single-ended inputs. The input common-mode voltage of the amplifier/comparator is input-dependent in a fully-differential input ADC. So single-ended inputs will affect the linearity of the amplifier/comparator, which requires the amplifier/comparator to have a wide input common-mode range. In the proposed circuit, the summing node is floating in the sampling phase to avoid sampling the common-mode voltage of input. And in order to preserve the linearity of sampling, the gate-source voltage of the top-plate short switch is kept almost unchanged by a bootstrap circuit. The proposed front-end circuit is implemented and validated in a 0.18μm CMOS process. At a sampling rate of 125Msps, the circuit achieves 84.4dBc SFDR when the single-ended input reaches Nyquist frequency with an amplitude of 2.2 V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PP</inf>.