Slew-Rate Analysis of Scalable Multi-Stage CMOS Operational Transconductance Amplifiers

This paper presents an in-depth analysis of the Slew-Rate (SR) in scalable multi-stage CMOS Operational Transconductance Amplifiers (OTAs). These OTAs utilize Low-Frequency (LF) zeros in their frequency compensation technique to address stability issues encountered when cascading gain stages in closed-loop configurations. However, the SR analysis of such OTAs deviates from conventional SR equations due to the presence of LF zeros. Hence, this paper explores the SR behavior of scalable OTAs and develops a new set of SR equations. These equations are validated and verified through simulations and measurement results. The proposed design is fabricated using a TSMC 65 nm CMOS process.