MSPARQ: A RISC-V Vector Processor Array Optimized for Low-Resolution Neural Networks

This paper explores using a multicore RISC- V vector processor to enhance the performance of convolutional neural networks (CNNs) quantized to low and ultra-low precisions. Optimizing CNNs' efficiency is crucial in resource-constrained environments such as embedded systems. To this end, we use Sparq, a 64-bit RISC-V RVV1.0 processor derived from “Ara”. This paper introduces MSPARQ, its multicore version developed using the OpenPiton framework and implemented in GlobalFoundries 22FDX FD-SOI technology. The performance of a CNN conv2d kernel is evaluated by emulating MSPARQ on a Xilinx Alveo U280 FPGA board. Results show that through an adequate mapping of this kernel, a 4-core configuration can achieve a speedup of 3.6 to 3.8 times over the single-core configuration, while sub-byte optimizations included in the Sparq core deliver an additional speedup by 2.1 and 1.8 times respectively for 1-bit and 2-bit precisions, over the 16-bit implementation of the conv2d operation.