Recent Research in Design and Technology Co-Optimization with Multi-Bit Flip-Flops

This paper surveys a number of noticeable recent research activities on the design and technology co-optimization (DTCO) with multi-bit flip-flop cells in design automation perspective. Multi-bit flip-flop (MBFF) cells are widely used for low-power design, but they incur a number of critical limitations which should be overcome. Those are, due to the grouping of individual flip-flops as well as the sharing of internal clock inverters, the layout space waste in MBFF cells, the inflexibility in optimizing interconnects, and the inflexibility in optimizing timing. Specifically, the DTCO research activities surveyed in this paper are (1) the utilization of the diverse structures of MBFF cells in optimizing interconnect, (2) the utilization of the empty space in MBFF cells in optimizing timing, and (3) the exploitation of debanking the MBFF cell instances to trade off power against timing.