Precise Trap Handler for a Pipelined 32-Bit Processor for Space Applications

In this paper, we present the design of a trap handler designed for in-house developed 32-bit pipelined processor. The trap handler can handle both interrupts and exceptions precisely and is compliant to IEEE 1754 std. The exceptions are handled such that the instruction which raises the exception and the subsequent instructions in the pipeline do not change the state of the processor. In the case of interrupts, the instructions in the different pipeline stages complete their execution before the interrupt controller is called upon. The context of the processor is saved correctly so that the processor can resume the program flow correctly after servicing the trap.