Low Temperature III-V and Si Wafer Bonding with Lateral Outgassing Channels

A direct wafer bonding condition for III-V and Si integration has been demonstrated, which employs lateral outgassing channel grids, manually mates wafers at atmospheric pressure and anneals at a relatively low temperature of 230°C.

Authors

Sushil Tandukar
Il‐Sug Chung (ORCID: https://orcid.org/0000-0002-6382-2795)
Sangmin Oh (ORCID: https://orcid.org/0000-0003-3319-983X)
Jaeseong Jeon

Institutions

Ulsan National Institute of Science and Technology (KR)

Publication Details

Published: 2024-08-04
DOI: https://doi.org/10.1109/cleo-pr60912.2024.10676891
Primary Topic: 3D IC and TSV technologies
Type: article
Field-Weighted Citation Impact: 0.00

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article

Low Temperature III-V and Si Wafer Bonding with Lateral Outgassing Channels

Sushil Tandukar, Il‐Sug Chung, Sangmin Oh, Jaeseong Jeon

Aug 4, 2024

3D IC and TSV technologies

article

Low Temperature III-V and Si Wafer Bonding with Lateral Outgassing Channels

Sushil Tandukar, Il‐Sug Chung, Sangmin Oh, Jaeseong Jeon

August 4, 2024article en

Abstract

Ulsan National Institute of Science and Technology (KR)

Affordable and clean energy

Openalex Percentile: Top 87%

3D IC and TSV technologies

DOI Source OpenAlex

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Low Temperature III-V and Si Wafer Bonding with Lateral Outgassing Channels — Sushil Tandukar, Il‐Sug Chung, et al. · (2024) | TGRS Research Map | TGRS