Ising Model Processors on a Spatial Computing Architecture

Data-flow-driven spatial computing architectures are emerging to enable efficient acceleration of complex machine learning models at the edge devices. Interestingly, their potential in other domains of computing is yet to be thor-oughly explored. Hence, this paper investigates the application of spatial architectures for designing reconfigurable Ising model processors on edge devices. We target AMD's Versal Adaptive SoCs platform and implement Ising model processors using the parallelization opportunities in the VLIW -supported vector processors arranged in a spatial configuration. Our experiments on a VCK-190 evaluation platform demonstrate that spatial computing implementation for the standard Metropolis algorithm achieves <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3\times$</tex> to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$9\times$</tex> speedup compared with a generic ARM Cortex A-72 processor for varying matrix sizes and precision. We also present implementation issues for design accelerators on Versal ASoCs. The code and artifacts for the work are available at https <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$://\text{github}$</tex>, com/SPIRE-GMU/Ising-AIE for reproducing the experiments and results presented in this work.