Design of Low-Voltage and Low-Power Cryogenic CMOS Voltage Reference Circuits

This paper presents the design of low-voltage and low-power cryogenic CMOS voltage reference circuits. This cryo-optimized circuit uses low-threshold devices to compensate for the transistors' threshold increase in ultra-low temperatures. Similarly, the PTAT factor is increased three times from its optimal value as compensation for the current decrease in cryogenic temperatures. A family of reference circuits was implemented in standard 65-nm CMOS. The silicon results show temperature coefficients of 419, 350, and 229 ppm/K in the ultra-wide temperature range from 4 to 295 K, with power consumptions at 4 K of only 5.3 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mu W, 22.7\mu W$</tex>, and 410 nW, respectively.