Throughput Optimization for Time-Domain Neuromorphic Computing

We present a low-power, low-area delay cell topology for time-domain (TD) neuromorphic computing. Each cell computes partial dot product operations using current summation and the result is accumulated by chaining delay cells together. An alternative clocking scheme for the delay chains is proposed that requires no additional area and can nearly 2x the throughput. In addition, the application of TD wave-pipelining is proposed to further improve throughput. These techniques were applied to a 64-input delay chain and to the design of a 3-input TD XOR gate. With the delay chain, up to a 11.54x speedup was observed. The proposed wave-pipelining provides larger speedups for longer delay chains, such as would be utilized by neural networks.