A Rail-to-Rail Low-Power Dynamic CMOS Amplifier for Switched-Capacitor Filters in High-Performance ADC

This paper presents a novel rail-to-rail low power dynamic CMOS amplifier optimized for discrete-time filtering in analog-to-digital converters (ADC). The proposed architecture incorporates a switched resistor-capacitor (RC) parallel compensation technique, which is strategically activated in the sampling phase to minimize the amplifier's current consumption. Dynamic biasing of the amplifier further improves energy efficiency by slashing high slewing currents once linear settling takes over. Simulation results in 65 nm CMOS exhibit 3.2 times reduction in power consumption with respect to a comparable static amplifier. Accurate integration waveforms are achieved while consuming a mere 239 μW for 6 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$T$</tex> settling under 4.9 ns.