RISC- Vcito: A Multicycle Tiny Processor Implemented with SKY130 PDK

This work provides a detailed account of the step-by-step process of creating RISC- V cito. The journey begins by designing the processor's inner workings at the Register Transfer Level (RTL), defining how it should function and perform. To ensure the processor's reliability, a thorough validation phase using the Universal Verification Methodology (UVM) is conducted. Open-source tools, such as Icarus Verilog, Yosys and GTKWave, have been used to inspect all aspects of RISC- V cito performance. Additionally, Cadence's Xcelium was utilized for verification. The article concludes by explaining how RISC- V cito was implemented with the SKY130 Process Design Kit (PDK) using OpenLane. This integration includes various physical design steps like synthesis, placement, and routing, resulting in the creation of a Graphic Design System (GDSII) file. This contribution provides valuable insights into using open-source tools for processor development, covering RTL design, UVM validation, and the transformation of the design into a GDSII file, ready for the manufacturing process. Open-source tools have the power to shape modern computer architecture, leading to tangible products for production.