Dynamic Clock Switching Scheme for Enhanced Power Efficiency in System-on-Chip Architectures

High power consumption and thermal management are critical challenges in traditional System- on-Chip (SoC) architectures due to multiple active clock sources feeding individual IP blocks, even during idle states. This paper introduces a dynamic clock switching power-saving scheme that consolidates clock sources by dynamically switching to a single lower-frequency clock during low-power modes. A Clock Control Agent (CCA) monitors real-time operational status, power consumption, and performance needs, leveraging AI for predictive adjustments. Experimental results demonstrate a significant reduction in idle power consumption and improved thermal management, without compromising performance or data integrity. This scheme addresses inefficiencies in existing methods such as Dynamic Voltage and Frequency Scaling (DVFS) and clock gating, offering a robust and efficient solution for next-generation SoC designs.