SYCL-based Acceleration of Canny Edge Detector Algorithm Using DPC++

Edge detection is a fundamental task in image processing which has proliferated into various fields. This paper presents a SYCL-based Data Parallel C++ (dpc++) implementation and evaluation of Canny Edge Detection (CED) in CPU-GPU and CPU-FPGA heterogeneous computing platforms. The CED accelerator was implemented and evaluated on two state-of-the-art Intel FPGAs, Arria 10 GX-1150 and Stratix 10 SX-2800 and an Intel GPU, UHD P630 with the Intel's CPU, Xeon Gold-6128. Along with a mathematical optimization, design optimizations specific to parallel computing were leveraged for efficiency and speedup. The evaluation of the implementation reports speedups of 11.6X and 11.7X for Arria 10 and Stratix 10 FPGAs respectively with respect to the CPU -only implementation. Also, both FPGAs completed the algorithm more than 4 times faster than the GPU. Furthermore, Arria 10 FPGA is 31 times more energy efficient than the GPU. Also compared to related research, significantly better speedup results were achieved by our im-plementation. With 0.214 milliseconds execution time to detect edges in an image with size 256x256 pixels, the recommended dimension for real-time image processing applications, our CPU-FPGA implementation is best suited for real-time applications