Invited Paper: A Pseudo-Differential Architecture for Low-Power Voltage-to-Time Converters

A new architecture for a pseudo-differential low-power voltage-to-time converter (LP-VTC) circuit is proposed. This LP-VTC architecture is compatible with a wide range of applications such as biomedical implants and integrated DC-DC voltage converters. In addition, it is used for time-based analog-to-digital converters (T-ADCs). T-ADC converts the analog noisy input signal into a time delay in the form of either a pulse position modulated (PPM) signal or a pulse width modulated (PWM) signal through the VTC circuit. Then, this time delay is converted into a digital code utilizing a time-to-digital converter (TDC) circuit. Low power consumption is achieved by using time-multiplexing, low supply voltage with supply control signals, and high threshold voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf>) transistors to eliminate the short circuit power (PSG) through the proposed design. A prototype of the proposed LP- VTC circuit is implemented in <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.13 \mu\mathrm{m}$</tex> CMOS technology where the analog blocks operate with an 0.8 V supply, whereas the digital blocks operate at a 0.6 V supply. Moreover, the proposed LP- VTC exhibits a wide linear input range with a 2 MS/s sampling rate.