Redundancy Based Resistor String DAC with an all Digital Calibration Algorithm

This paper presents a novel3-segment interpolating resistor string ladder DAC with sub-radix/redundancy characteristics in the DAC transfer curve. A simple all-digital calibration algorithm is presented which trades off resolution for linearity. The design is shown to reduce the area overhead significantly compared to the conventional resistor string DAC. A 15-bit version of the DAC using poly-resistors is designed in the TSMC 180nm process and the calibration algorithm implemented in MATLAB to obtain a 13-bit linear DAC with a worst case INL of 0.78LSBs across 100 Monte-Carlo iterations with resistor matching at only the 5-bit level.