Design and Analysis of 4x4 bit various Multiplier Using Look-up table and implementation in FIR Filter

In the comparison of 4 x 4 multiplier according to time, area, and speed, Look-Up Tables (LUTs) are used to meet high speed and low power requirements, which are essential in VLSI. In the implementation of Wallace tree, Booth, array multipliers, to identify the most efficient one considering all VLSI aspects. Wallace tree multipliers and Booth multipliers are more effective than array multipliers in terms of delay and power consumption, which makes them more appropriate in area while sacrificing in speed.. But the Wallace tree multiplier is more suitable for FIR filters than other filters. The Xilinx ISE tool is used to implement Verilog code for generating schematic views of the multipliers, highlighting time, speed, and area characteristics.The FIR filter is implemented using MATLAB software.