A 5T-SRAM Based Computing-in-Memory Macro Featuring Partial Sum Boosting and Analog Non-Uniform Quantization

Analog computing-in-memory (CIM) macro has been widely used in various machine learning (ML) applications, which parallelly perform energy- and area-efficient matrix-vector multiplication (MVM) operations. Compared with digital CIM, analog CIM has shown great efficiency on multi-bit MVM computations. However, the analog approaches accumulate the MVM results on the voltage domain, different accumulation lengths and data sparsity cause distinct signal swing degradation and variation. Hence, the analog-to-digital converter (ADC) readout circuit requires more power and area to trade off with the noise and comparator offset. In this paper, we proposed a partial sum boosting (PSB) method to give <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4.6\times$</tex> to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$22.8\times$</tex> signal swing enhancement for multi-bit MVM, which mitigates severe ADC overhead for analog CIM. Furthermore, multi-bit 5T-SRAMs with diverse voltage supplies realize multi-bit uniform/non-uniform sign-and-magnitude (SNM) weight representation and save up to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$38.8\times$</tex> SRAMs static power dissipation. The chip was fabricated in 28nm CMOS technology and measured a throughput density of 89.04 TOPS <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$/\text{mm}^{2}$</tex> and energy efficiency of 219.5 TOPSIW under 3-bit activation, 4-bit SNM weight with no truncation 5-bit partial sum readout condition.