Analysis and Design of a Compute-in-Memory System for Epileptic Seizure Detection System

This paper presents an area and power-efficient design of a dual-channel electroencephalogram (EEG) based digital processor that can identify the onset of seizures with high accuracy. Multiple modules, including feature extraction and classification, constitute the hardware design. Neural networks are employed as classifiers because of their exceptional performance. These networks are data-driven algorithms that cause the system's performance to deteriorate and its power consumption to increase. A compute-in-memory (CIM) architecture has thus been used to address this problem. The performance of the neural network algorithm is evaluated using an open-source database of CHBMIT with 87.1% accuracy, 91.2% sensitivity, and 90.5% specificity. In contrast, the performance of hardware architecture was evaluated using its power, area, and latency. The synthesis and implementation were carried out using the 0.18µm CMOS process. A comparison of two architectures, the fixed point neural network architecture and the CIM neural network architecture, clearly indicated that the CIM processor performed significantly better in terms of power and area while sacrificing latency because of bit serial computing. To detect seizures in real-time, the CIM processor consumes 241µJ/classification while the fixed-point neural network consumes 256µJ/classification of energy.