A 10 MHz to 3.2 GHz Differential Current Starved Inverter-Based Self-Biased Adaptive Bandwidth PLL in 65nm CMOS

Adaptive bandwidth PLLs offer optimized noise and jitter performance but require active feedback compensation. We present a differential inverter-based self-biased PLL with active feedforward zero placement. Our approach is simple to implement in scaled CMOS processes and achieves a FoM of -222 dB with an integrated jitter of 4.1 ps in a 100 MHz bandwidth while consuming only 3.72 mW for an output frequency of 1.92 GHz in 65nm LP CMOS. The PLL has a wide frequency range of 10MHz - 3.2 GHz. Furthermore, the physical design was done using place and route tools, unlike classical analog PLLs.