A 17 dB High Gain 65% PAE Wideband CMOS Integrated Power Amplifier Design in 180 nm Process for Wireless Power Transfer Applications

This paper presents the design of a high gain, high power added efficiency (PAE) wideband power amplifier (PA) in the standard 180nm CMOS process for wireless power transfer (WPT) applications. The proposed PA design utilizes a single stage common-source architecture, working in the ultra-wideband (UWB) frequency range (3.1 - 10.6 GHz). The amplifying stage utilizes a single NMOS transistor where the scaling factor of the transistor is optimized to generate the highest transconductance, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$g_{m}$</tex> value, and thus maximize the available power gain from the transistor. An analysis and optimization of the scaling factor is also performed to generate the optimal balance between achieving a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{high} \ g_{m}$</tex> while also minimizing the insertion loss from the quality factor of the integrated on-chip inductor so that a higher overall gain can be achieved. The designed PA achieves a maximum gain of 17.4 dB at 6.5 GHz frequency and the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$P_{1dB}$</tex> compression point occurs at an input power of 7 dBm. In addition, a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$-3\mathbf{dB}S_{21}$</tex> gain bandwidth of 2.19 GHz (5.29 - 7.48 GHz) can be obtained from the proposed PA design. At the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$P_{1dB}$</tex> compression point, the PA is able to generate an output power of 24.4 dBm at 6.5 GHz frequency for 3.3 V drain supply voltage. The proposed PA is able to achieve a peak PAE performance of 65.6% at the 16 dBm input power. By employing a single stage L-shaped shunt inductor and series capacitor as part of the input and output matching network, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&gt; 60\%$</tex> PAE performance is achieved over a wide bandwidth of 2 GHz from 5.5 - 6.5 GHz.

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Published
2024-08-11
DOI
https://doi.org/10.1109/mwscas60917.2024.10658706
Citations
1
Primary Topic
Wireless Power Transfer Systems
Type
article
Field-Weighted Citation Impact
0.21

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article

A 17 dB High Gain 65% PAE Wideband CMOS Integrated Power Amplifier Design in 180 nm Process for Wireless Power Transfer Applications

Ifana Mahbub, Rafsan Mahin
1 citations
Wireless Power Transfer Systems
0.21
article

A 17 dB High Gain 65% PAE Wideband CMOS Integrated Power Amplifier Design in 180 nm Process for Wireless Power Transfer Applications

Ifana Mahbub, Rafsan Mahin
article en
1 citations

Abstract

This paper presents the design of a high gain, high power added efficiency (PAE) wideband power amplifier (PA) in the standard 180nm CMOS process for wireless power transfer (WPT) applications. The proposed PA design utilizes a single stage common-source architecture, working in the ultra-wideband (UWB) frequency range (3.1 - 10.6 GHz). The amplifying stage utilizes a single NMOS transistor where the scaling factor of the transistor is optimized to generate the highest transconductance, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$g_{m}$</tex> value, and thus maximize the available power gain from the transistor. An analysis and optimization of the scaling factor is also performed to generate the optimal balance between achieving a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{high} \ g_{m}$</tex> while also minimizing the insertion loss from the quality factor of the integrated on-chip inductor so that a higher overall gain can be achieved. The designed PA achieves a maximum gain of 17.4 dB at 6.5 GHz frequency and the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$P_{1dB}$</tex> compression point occurs at an input power of 7 dBm. In addition, a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$-3\mathbf{dB}S_{21}$</tex> gain bandwidth of 2.19 GHz (5.29 - 7.48 GHz) can be obtained from the proposed PA design. At the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$P_{1dB}$</tex> compression point, the PA is able to generate an output power of 24.4 dBm at 6.5 GHz frequency for 3.3 V drain supply voltage. The proposed PA is able to achieve a peak PAE performance of 65.6% at the 16 dBm input power. By employing a single stage L-shaped shunt inductor and series capacitor as part of the input and output matching network, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$&gt; 60\%$</tex> PAE performance is achieved over a wide bandwidth of 2 GHz from 5.5 - 6.5 GHz.

The University of Texas at Dallas (US)
Defense Advanced Research Projects Agency
Affordable and clean energy
Openalex Percentile: Top 48%
Wireless Power Transfer Systems
0.21
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