VLSI Implementation of an Efficient 2D Median Finding Algorithm for Non Linear Image Filtering

This paper proposes an efficient architecture of two dimensional (2-D) Modified shear sorting architecture which produces median output based on pixels given in a window of M X N. The Architecture is built using an 8 bit data comparator. The Data comparator is implemented using a De-multiplexer based full subtractor. The Architecture is synthesized using Vivado 2023.2. The Implementation results show that the proposed architecture operates at power of 0.142 W in Spartan 7 FPGA device in comparison with the architectures reported. The delay of the architecture is 20.665 ns with a look up table (LUT) count of 235. Placing and routing layouts has been done using the Vivado tool.