IBM z16 Modular Scalable Cache Hierarchy and Future Concept Applications

The IBM Z® platform is optimized for processing vast amounts of data and transactions with low latency in a highly virtualized and secured environment. The platform and its microprocessor chip are designed to deliver consistent system performance, throughput, and response times with sustained processor utilization of over 90%. The IBM z16™ design introduced a novel modular scalable cache hierarchy to the industry that is extendable to future platform generations, the adoption of emerging technologies, and new architecture enhancements to meet the needs of the mission critical workloads that run on the platform. This paper will expand on prior publications discussing this novel design, demonstrate how events flow in the system, and explore the intersection of potential future architectures and technologies that could be integrated into this type of framework from an academic perspective.

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Publication Details

Published
2024-08-11
DOI
https://doi.org/10.1109/mwscas60917.2024.10658848
Primary Topic
Parallel Computing and Optimization Techniques
Type
article
Field-Weighted Citation Impact
0.00
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article

IBM z16 Modular Scalable Cache Hierarchy and Future Concept Applications

C. R. Walters
Parallel Computing and Optimization Techniques
article

IBM z16 Modular Scalable Cache Hierarchy and Future Concept Applications

C. R. Walters
article en

Abstract

The IBM Z® platform is optimized for processing vast amounts of data and transactions with low latency in a highly virtualized and secured environment. The platform and its microprocessor chip are designed to deliver consistent system performance, throughput, and response times with sustained processor utilization of over 90%. The IBM z16™ design introduced a novel modular scalable cache hierarchy to the industry that is extendable to future platform generations, the adoption of emerging technologies, and new architecture enhancements to meet the needs of the mission critical workloads that run on the platform. This paper will expand on prior publications discussing this novel design, demonstrate how events flow in the system, and explore the intersection of potential future architectures and technologies that could be integrated into this type of framework from an academic perspective.

Vol. 16
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Parallel Computing and Optimization Techniques
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