A Reading Method for 2T2R RRAM Arrays Coding their Multiple States
Resistive random-access memory (RRAM) devices have been frequently mentioned considering their robust performances. The conventional transistor one-memristor (1TIR) RRAM device becomes less competitive considering its multi- level operation. This paper introduces a two-transistor two- memristor (2T2 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$R$</tex>) structure as well as a reading method for the configuration. The designed sense circuit based on a Strong-Arm latch codes 9 different states with 6 bits in 48ns and consumes a power of 7.6uW and it also demonstrates a tolerance to RRAM technologies and variations.
Authors
- Amelie Hagelauer (ORCID: https://orcid.org/0000-0001-9113-9531)
- Running Guo
- Stefan Pechmann (ORCID: https://orcid.org/0000-0001-6890-3378)
Institutions
- Technical University of Munich (DE)
Publication Details
- Published
- 2024-08-11
- DOI
- https://doi.org/10.1109/mwscas60917.2024.10658733
- Primary Topic
- Advanced Memory and Neural Computing
- Type
- article
- Field-Weighted Citation Impact
- 0.00