A Sub-Sampling Front-End with 12 fF Load for On-Chip Measurements

A sub-sampling front-end with a low capacitive loading followed by a second order <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\Sigma\Delta$</tex> ADC is presented. The front end is designed in the UMC 65nm low-power CMOS process and has a power consumption of 110 µW from a 1.2 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V$</tex> supply. The ADC has a simulated SQNR of around 74 dB and an ENOB of around 12 bits. The time constant of the sampling front-end comes to nearly 0.76 ps. The entire front end occupies an area of 200 µm x 550 µm.