A Comparative Study of Dynamic Comparators in Low-Voltage SAR ADC

This paper provides a comparative study of dynamic comparators in low-voltage successive approximation register (SAR) analog-to-digital converters (ADCs). The architecture, comparison time, and power consumption of four widely used dynamic comparators are studied first. It is followed with an investigation of kickback in these comparators. We show although clock kickback is common-mode, the impedance asymmetry of the digital-to-analog converter (DAC) of SAR ADCs arising from the different channel resistances of DAC switches and manifesting itself only when supply voltage is low gives rise to a differential clock kickback that occurs earlier than output regeneration kickback with more strength and dictates the kickback of dynamic comparators. The dependence of the clock kickback on the input of SAR ADCs in least significant bit (LSB) conversion where the input is the smallest is investigated. The offset voltage of the dynamic comparators and its dependence on supply voltage are also investigated.