Python-Based DRAM Memory Controller Testbench: Pyuvm an Early Report

With Hardware Verification being regarded as a time-consuming complex task. Moreover, new design applications Such as machine learning are posing new challenges to hardware verification engineers. Adding on top of the above challenges the fact that the Universal Verification Methodology (UVM) has a class library that can be considered bloated. Python was suggested as an alternative to SystemVerilog, which is currently the main Hardware Verification language (HVL), used for building modern testbenches. Firstly, Cocotb was introduced almost ten years ago, then Pyuvm under two years ago. Python verification initiatives promise it is easier to learn( than traditional SystemVerilog), faster, and more productive to write. In this paper we explore the process of writing Python-based testbench, through writing DDR3 SDRAM Controller testbench. The testbench is implemented using the Pyuvm methodology running on top of Cocotb that’s used to interact with the Design under test (DUT). The motivation of this paper is to explore the capabilities of Python based verification, and how much of similarity or difference it does bear compared to traditional SystemVerilog and UVM.