A 0.92-pJ/b PAM-4 and 0.61-pJ/b PAM-6 224-Gb/s DAC-Based Transmitter in 3-nm FinFET

This article presents the architecture, circuit design, and measurement results of a 224-Gb/s transmitter (TX) based on a 7-bit digital-to-analog converter (DAC) driver with nine-tap digital feed-forward equalizer (FFE) fabricated in the 3-nm FinFET technology. The TX uses quarter-rate 28-GHz clocking for a combined single-stage, current-mode 4:1 multiplexer (MUX), and output driver, with a replica driver for phase adaptations. An LC-phase-locked loop (PLL) with a tuning range of 21.2–30.0 GHz allows to operate the TX at both four-level (PAM-4) and six-level (PAM-6) pulse amplitude modulation. The TX achieves 1-Vppd swing and analog energy efficiency of 0.92 pJ/b in PAM-4 and 0.61 pJ/b in PAM-6 while showing 36.0-dB SNDR, 55-mUI J3u03, and 62-fsrms jitter. To the best of the authors’ knowledge, the design achieved the highest energy efficiency to date at 224 Gb/s while complying with the IEEE 802.3ck Ethernet specifications scaled to 112 Gbaud.