An Ultra-Low-Voltage Bias-Current-Free Fractional-N Hybrid PLL With Voltage-Mode Phase Detection and Interpolation

This article presents an ultra-low voltage (ULV) fractional-N hybrid phase-locked loop (PLL) without requiring bias current. A time-interleaved flip-flop phase detector (TI-FFPD) with duty-cycle-based phase detection is employed to achieve high linearity and low reference spur. A passive-intensive voltage-mode phase interpolator (VPI) with a supply-immune voltage scaling topology is proposed for <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> quantization noise (Q-noise) reduction without gain or linearity calibration. A hybrid PLL (HPLL) that consists of a pseudo-differential analog proportional path and a digital integral path is implemented in 28-nm CMOS. The HPLL exhibits 607-fsrms jitter and −59-dBc in-band fractional spur at 2.42-GHz output and consumes 0.78-mW power from a 0.5-V supply, achieving the best figure of merit (FoMJIT) of −245.4 dB among low-voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V_{\mathrm {DD}}}~{\lt }~0.8$ </tex-math></inline-formula> V) fractional-N PLLs.