An Embedded Module of Enhanced Turbo Product Code Algorithm

Low density parity check code (LDPC) is the most popular error correction code (ECC) for current nand flash memory controllers. Next generation flash memory, such as triple-level cell (TLC) and quad-level cell (QLC) with a higher bit error rate, bring up the demand for superior ECC algorithms providing excellent performance and acceptable hardware overhead. This letter proposes turbo product code (TPC) as an alternative to LDPC by exploring embedding of a TPC engine into a solid-state drive (SSD) controller architecture. The implementation of this TPC engine uses 2-D error coding and applies the Bose-Chaudhuri–Hocquenghem (BCH) code in each dimension. The algorithm is further improved by flipping the dedicated bit matrix when the basic TPC decoding algorithm terminates with uncorrectable conditions. This bit-flipping enhanced TPC (BFE-TPC) module is finally integrated into a nonvolatile memory express (NVMe) SSD controller driving eight flash memory channels. This BFE-TPC module illustrates the potential of 2D-TPCs as a replacement for LDPCs due to its high throughput and low hardware overhead.