A 23.2-to-26-GHz Low-Jitter Fast-Locking Sub-Sampling PLL Based on a Function-Reused VCO-Buffer and a Type-I FLL With Rapid Phase Alignment

This article presents a type-II sub-sampling phase-locked loop (SSPLL) that achieves low jitter, low spur, and sub-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>s locking time when synthesizing millimeter-wave (mm-wave) frequencies. The proposed function-reused (FR) voltage-controlled oscillator (VCO)-buffer eliminates the noise and capacitive loading from the transistors in the buffer, improving the jitter and reference (ref.) spur of the SSPLL simultaneously. It also eliminates the inductor typically employed in the high-frequency buffer, reducing the chip area. The proposed low-power fast frequency-locked loop (FLL) utilizes a phase aligner to decouple the dependency of the locking time on the initial phase error. The FLL also employs a coarse-fine-time-to-digital converter (TDC)-based type-I loop for promptly searching the control word of the switched capacitors (SCs). This article also details the analysis of the ref. spur and the phase noise (PN) performance using the FR VCO-buffer as well as the design considerations of the proposed FLL. Fabricated in 28-nm CMOS, the SSPLL occupies a compact area of 0.065 mm2 and achieves an rms jitter of 48.3 fs at 26 GHz while consuming 19.1 mW, corresponding to excellent FoMJ and FoMN of −253.5 and −277.6 dB, respectively. The measured ref. spur is −66 dBc, and the measured locking time at a frequency jump from 0.4 to 2.8 GHz is within 55 ref. cycles.